1. Field of the Invention
The present invention relates to thin dielectric layers used in integrated circuit devices such as the dielectric layers provided between electrodes of charge storage capacitors used in some integrated circuit devices.
2. Description of the Related Art
Integrated circuit memory devices often include capacitors which are charged to different levels to represent stored data. For example, dynamic random access memories (DRAMs) typically consist of an array of memory cells with each memory cell including a charge storage capacitor connected to one source/drain region of a transfer field effect transistor (FET). One or another of two different charge levels is provided on the electrodes of the charge storage capacitor to represent either a logical one or zero stored in the memory cell. The transfer FET acts as a switch for selectively coupling a terminal electrode of the charge storage capacitor to data lines and other circuitry during data reading or writing operations.
DRAM charge storage capacitors consist of two electrodes separated by a layer of dielectric material. Most often, at least the surfaces of the electrodes that are in contact with the layer of dielectric material are doped polysilicon. The lower electrode or terminal of the charge storage capacitor is most often a polysilicon structure having a lower surface formed in contact with a source/drain region of the transfer FET. Often, portions of the lower electrode extend onto an insulating layer formed over other portions of the transfer FET and adjacent other portions of the DRAM. The lower capacitor electrode might have a planar surface, but more commonly the lower electrode has a surface with a more complicated shape including, for example, one or more fins extending from a base part of the electrode. Whether or not the lower electrode of the capacitor has such a complicated shape, the upper electrode of the capacitor is made so that its surface is in close, spaced parallel relationship to the surface of the lower electrode. Such a close, spaced parallel relationship is easily provided by first forming a thin dielectric layer over the surface of the lower electrode and then conformally depositing the upper electrode onto the dielectric layer.
It is almost always desirable for charge storage capacitors to be capable of high levels of charge storage, i.e., charge storage capacitors preferably have comparatively high levels of capacitance. Capacitance is determined in part by the distance separating the upper and lower electrodes that make up the charge storage capacitor. Since the upper electrode is separated from the lower electrode by the dielectric layer, the spacing between the upper and lower electrodes is typically determined by the thickness of the dielectric layer. Another factor affecting capacitance is the dielectric constant of the layer of dielectric material which separates the electrodes of the charge storage capacitor. Use of higher dielectric constant materials as the capacitor dielectric increases the amount of charge that can be stored on the charge storage capacitor.
Other characteristics of capacitor performance, less directly related to capacitance, are also affected by the particular material chosen for the dielectric layer within the capacitor. These include both the rate at which charge leaks across the layer of dielectric material in a given implementation and the breakdown voltage, that is, the voltage applied across the capacitor electrodes at which the dielectric material undergoes dielectric breakdown. Both charge leakage and breakdown voltage are factors not only of the particular material chosen, but also of the quality of the films of that material that can be formed and used compatibly with high volume manufacturing processes. For example, if a thin layer of a given capacitor dielectric material cannot be formed without pinholes of the type associated with charge leakage, then that dielectric material may be undesirable for use in capacitors. Similarly, if a given capacitor dielectric material has a low breakdown voltage, then the capacitor dielectric material may only be suited for use in low operating voltage applications.
One commonly used dielectric for DRAM charge storage capacitors consists of a three layer structure of a first layer of silicon oxide, a middle layer of silicon nitride and a second or upper layer of silicon oxide on the other side of the silicon nitride layer. This dielectric structure is commonly referred to as "ONO". Most of the thickness of the ONO structure consists of the middle silicon nitride layer so that the ONO structure has a dielectric constant largely determined by the comparatively high dielectric constant of the silicon nitride. The effective dielectric constant of the structure is reduced by the lower dielectric constant of the oxide layers which are capacitively in series with the silicon nitride layer. Typically, the lower layer of silicon oxide is a native oxide on the surface of the polysilicon of the lower capacitor electrode which is difficult to eliminate. The upper layer of silicon oxide is formed to provide a better surface for the deposition of the polysilicon layer of the upper electrode than is provided by the silicon nitride layer.
ONO dielectric layers are typically grown on N-type polysilicon lower electrodes of DRAM charge storage capacitors through a series of thermal processing steps performed in different gas ambients. Various types of thermal reaction furnaces might be used for growing the ONO dielectric structure. Substrates ready for dielectric formation have undergone a series of processing steps including the formation of an array of transfer FETs and a corresponding array of doped polysilicon lower electrodes. Prior to growing the dielectric layer, the substrates, typically silicon wafers, are held adjacent the reaction chamber and the chamber reaches a temperature of about 400.degree. C. in a nitrogen (N.sub.2) ambient. One or more substrates are then moved into the reaction chamber, and the temperature is ramped up to 700.degree. C. while still maintaining the nitrogen ambient. A layer of thermal oxide of about 12-18 .ANG. grows on the surface of the polysilicon lower electrode during the processing steps up to this point. After the temperature has stabilized at 700.degree. C., a mixture of NH.sub.3 (180 sccm) and SiH.sub.2 Cl.sub.2 (36 sccm) flows into the reaction chamber at a pressure of about 100 mTorr. This process is continued to grow a silicon nitride layer of the desired thickness, typically 40-80 .ANG., and the gas flow is stopped. Next, the temperature is ramped down from 700.degree. C. to a temperature of about 400.degree. C. in a nitrogen ambient and then the substrate is removed from the reaction chamber. The substrate is then placed in another reaction chamber and heated to a temperature of about 850.degree. C. for 15-30 minutes in a steam or wet O.sub.2 environment to grow a surface layer of silicon oxide. The silicon oxide layer formed on the surface of the silicon nitride layer is thin due to the difficulty in oxidizing the surface of silicon nitride.
The lower layer of silicon oxide in ONO dielectric films is undesirable for a number of reasons. Due to the lower dielectric constant of silicon oxide as compared to silicon nitride, the presence of the silicon oxide in series with the silicon nitride layer acts to reduce the capacitance of the capacitor. Furthermore, the thickness of the lower silicon oxide layer is variable and difficult to control. Variations in the thickness of the silicon oxide layer can result in undesirable variations in device performance. Accordingly, it is desirable to provide a more reliable and predictable dielectric for capacitors in integrated circuits.
As DRAM cell density increases, it is necessary to form DRAM capacitors having reduced dimensions while still retaining an acceptable level of capacitance. One method of maintaining the desired level of capacitance is to use thinner capacitor dielectric films. There is considerable difficulty, however, in forming ONO dielectric films as thin as is desirable for reduced dimension DRAM charge storage capacitors. In addition, thin ONO films have undesirably low breakdown voltages for such reduced dimension charge storage capacitors. More reliable thin dielectric films are therefore desirable for DRAM capacitors. It would be desirable to utilize materials having higher a dielectric constant for the DRAM capacitor dielectric, but such materials remain unpredictable and unreliable.